The advance of the technology gives the ability to integrate a large number of cores on a single chip. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. To evaluate and analyse the performance metrics of on-chip networks under different scenarios (e.g. various Traffic Patterns/ Topology / Routing / Flow Control).

Chris Ok', London UK